Machine Learning Routes Chips

SANTA ROSA, Calif.—The future of chip routing will be covered by the fastest machine learning methods—gone are auto-routing algorithms for billion transistors chips, according to the International Symposium of Physical Design 2016 (ISPD, 2016, April 3-6, Santa Rosa, Calif.) ISPD 2016 concluded its sessions with award ceremonies for best solution to its annual design contest and its best-paper awards, which featured machine learning of a power distribution network. The ISPD 2016 contest was for the first time a routing problem for interconnecting a field-programmable gate array (FPGA). With Xilinx as the sponsor, the contest involved using a Xilinx XCVU095 FPGA, a part in the 20-nanometer Virtex UltraScale family (the XCVU095 has 67,200 configurable logic blocks (CLBs), 880 input/output (I/O) locations, 770 multiplier (DSP) locations, and 1730 block random access memory…


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